16f884 CPU configuration

Each attribute in the configuration table below has two or more possible values associated with it.

e.g. the watchdog attribute (labelled field J ) has the possible values

one and only one of these values must be specified when configuring the CPU

The 16f884 CPU has 13 configuration attributes (labelled field A to M in the table below). The attributes specific to the 16f884 CPU are defined in the file hwreg-p16f884.h To correctly configure the 16f884 CPU each attribute must be set to a valid value. This is done by using one "pragma cpu_config" statement per attribute. A valid configuration for 16f884 would look like: 

e.g.
	include "hwreg-p16f884.h"

	pragma cpu_config CFG_DEBUG_ON
	pragma cpu_config CFG_LVP_ON
	pragma cpu_config CFG_FCMEN_ON
	pragma cpu_config CFG_IESO_ON
	pragma cpu_config CFG_BOR_ON
	pragma cpu_config CFG_CPD_ON
	pragma cpu_config CFG_CP_ON
	pragma cpu_config CFG_MCLRE_ON
	pragma cpu_config CFG_PWRTE_ON
	pragma cpu_config CFG_WDT_ON
	pragma cpu_config CFG_LP_OSC
	pragma cpu_config CFG_WRT_OFF
	pragma cpu_config CFG_BOR21V

NOTE: All attributes for a given processor must be specified, attributes for different processors may not be mixed.

Field
Attribute
XCSB value
Description
A
 In Circuit Debugging CFG_DEBUG_ON In Circuit Debugger disabled
RB6 and RB7 are general purpose I/O pins
CFG_DEBUG_OFF In Circuit Debugger enabled
RB6 and RB7 are dedicated to the debugger
B
 Low Voltage In-Circuit Programming CFG_LVP_ON Low Voltage in-circuit serial Programming enabled
RB3/PGM pin has PGM function
CFG_LVP_OFF Low Voltage in-circuit serial Programming disabled
RB3/PGM pin has digital I/O function
(high voltage must be present on MCLR pin for programming)
C
   CFG_FCMEN_ON Fail-Safe Clock Monitor enabled
CFG_FCMEN_OFF Fail-Safe Clock Monitor disabled
D
   CFG_IESO_ON internal external switch over mode enabled
CFG_IESO_OFF internal external switch over mode disabled
E
   CFG_BOR_ON BOR enabled
CFG_BOR_NSLEEP BOR enabled during operation and disabled in Sleep
CFG_BOR_SBODEN BOR controlled by SBOREN bit of the PCON register
CFG_BOR_OFF BOR disabled
F
 Data EEPROM code protect CFG_CPD_ON data memory code protection enable
CFG_CPD_OFF data memory code protection disable
G
 Program Memory Code Protect CFG_CP_ON program memory code protection enable
CFG_CP_OFF program memory code protection disable
H
   CFG_MCLRE_ON RE3/MCLR pin function is digital I/O, MCLR internally tied to VDD
CFG_MCLRE_OFF RE3/MCLR pin function is MCLR
I
 Power-Up Timer CFG_PWRTE_ON power-up timer enable
CFG_PWRTE_OFF power-up timer disable
J
 Watchdog timer CFG_WDT_ON watchdog timer enable
CFG_WDT_OFF watchdog timer disable and can be enabled by SWDTEN bit of the WDTCON register
K
 Oscillator CFG_LP_OSC Low Power Crystal (LP) oscillator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
CFG_XT_OSC Crystal / Resonator (XT) oscillator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
CFG_HS_OSC High Speed Crystal / Resonator (HS) oscillator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
CFG_EC_OSC I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
CFG_INTRC_OSC_NOCLKOUT I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
CFG_INTRC_OSC_CLKOUT CLKOUT function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
CFG_EXTRC_OSC_NOCLKOUT CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
CFG_EXTRC_OSC_CLKOUT I/O function on RA6/OSC2/CLKOUT pin, RC on RA7/OSC1/CLKIN
CFG_INTOSCIO same as CFG_INTRC_OSC_NOCLKOUT
CFG_INTOSC same as CFG_INTRC_OSC_CLKOUT
CFG_EXTRCIO same as CFG_EXTRC_OSC_NOCLKOUT
CFG_EXTRC same as CFG_EXTRC_OSC_CLKOUT
L
   CFG_WRT_OFF write protection off
CFG_WRT_256 0x0000 to 0x00FF write is protected, 0x0100 to 0x0FFF may be modified under EECON control
CFG_WRT_1FOURTH 0x0000h to 0x03FF write is protected, 0x0400 to 0x0FFF may be modified under EECON control
CFG_WRT_HALF 0x0000 to 0x07FF write is protected, 0x0800 to 0x0FFF may be modified under EECON control
M
   CFG_BOR21V brown-out reset set to 2.1V
CFG_BOR40V brown-out reset set to 4.0V