Each attribute in the configuration table below has two or more possible values associated with it.
e.g. the watchdog attribute (labelled field J ) has the possible values
one and only one of these values must be specified when configuring the CPU
- CFG_WDT_ON
- CFG_WDT_OFF
The 16f88 CPU has 13 configuration attributes (labelled field A to M in the table below). The attributes specific to the 16f88 CPU are defined in the file hwreg-p16f88.h To correctly configure the 16f88 CPU each attribute must be set to a valid value. This is done by using one "pragma cpu_config" statement per attribute. A valid configuration for 16f88 would look like:
e.g. include "hwreg-p16f88.h" pragma cpu_config CFG_CP_ALL pragma cpu_config CFG_CCP1_RB0 pragma cpu_config CFG_DEBUG_ON pragma cpu_config CFG_WRT_PROTECT_NONE pragma cpu_config CFG_CPD_ON pragma cpu_config CFG_LVP_ON pragma cpu_config CFG_BODEN_ON pragma cpu_config CFG_MCLRE_ON pragma cpu_config CFG_PWRTE_ON pragma cpu_config CFG_WDT_ON pragma cpu_config CFG_EXTRC_CLKOUT pragma cpu_config CFG_IESO_ON pragma cpu_config CFG_FCMEN_ONNOTE: All attributes for a given processor must be specified, attributes for different processors may not be mixed.
Field Attribute XCSB value Description A Program Memory Code Protect CFG_CP_ALL code protect all program memory CFG_CP_OFF do not code protect any program memory B CFG_CCP1_RB0 CCP1 function on RB0 CFG_CCP1_RB3 CCP1 function on RB3 C In Circuit Debugging CFG_DEBUG_ON In Circuit Debugger disabled
RB6 and RB7 are general purpose I/O pinsCFG_DEBUG_OFF In Circuit Debugger enabled
RB6 and RB7 are dedicated to the debuggerD Program memory write protect CFG_WRT_PROTECT_NONE No prog memory write protection CFG_WRT_PROTECT_256 First 256 prog memory write protected CFG_WRT_PROTECT_2048 First 2048 prog memory write protected CFG_WRT_PROTECT_ALL ALL prog memory write protected E Data EEPROM code protect CFG_CPD_ON Data EEPROM is code protected CFG_CPD_OFF Data EEPROM is not protected F Low Voltage In-Circuit Programming CFG_LVP_ON Low Voltage in-circuit serial Programming enabled
RB3/PGM pin has PGM functionCFG_LVP_OFF Low Voltage in-circuit serial Programming disabled
RB3/PGM pin has digital I/O function
(high voltage must be present on MCLR pin for programming)G Brown-Out Reset CFG_BODEN_ON Brown-Out Reset enabled CFG_BODEN_OFF Brown-Out Reset disabled H CFG_MCLRE_ON RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD CFG_MCLRE_OFF RA5/MCLR pin function is MCLR I Power-Up Timer CFG_PWRTE_ON power-up timer enable CFG_PWRTE_OFF power-up timer disable J Watchdog timer CFG_WDT_ON watchdog timer enable CFG_WDT_OFF watchdog timer disable K Oscillator CFG_EXTRC_CLKOUT EXTRC oscillator; CLKO function on RA6/OSC2/CLKO CFG_EXTRC_IO EXTRC oscillator; port I/O function on RA6/OSC2/CLKO CFG_INTRC_CLKOUT INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin CFG_INTRC_IO INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin CFG_EXTCLK EXTCLK; port I/O function on RA6/OSC2/CLKO CFG_HS_OSC High Speed Crystal / Resonator (HS) oscillator CFG_XT_OSC Crystal / Resonator (XT) oscillator CFG_LP_OSC Low Power Crystal (LP) oscillator L CFG_IESO_ON Internal External Switch Over mode enabled CFG_IESO_OFF Internal External Switch Over mode disabled M CFG_FCMEN_ON Fail-Safe Clock Monitor enabled CFG_FCMEN_OFF Fail-Safe Clock Monitor disabled