16f737 CPU configuration

Each attribute in the configuration table below has two or more possible values associated with it.

e.g. the watchdog attribute (labelled field H ) has the possible values

one and only one of these values must be specified when configuring the CPU

The 16f737 CPU has 12 configuration attributes (labelled field A to L in the table below). The attributes specific to the 16f737 CPU are defined in the file hwreg-p16f737.h To correctly configure the 16f737 CPU each attribute must be set to a valid value. This is done by using one "pragma cpu_config" statement per attribute. A valid configuration for 16f737 would look like: 

e.g.
	include "hwreg-p16f737.h"

	pragma cpu_config CFG_CP_ALL
	pragma cpu_config CFG_CCP2_RC1
	pragma cpu_config CFG_DEBUG_ON
	pragma cpu_config CFG_VBOR_2_0
	pragma cpu_config CFG_BOREN_1
	pragma cpu_config CFG_MCLR_ON
	pragma cpu_config CFG_PWRTE_ON
	pragma cpu_config CFG_WDT_ON
	pragma cpu_config CFG_EXTRC_CLKOUT
	pragma cpu_config CFG_BORSEN_1
	pragma cpu_config CFG_IESO_ON
	pragma cpu_config CFG_FCMEN_ON

NOTE: All attributes for a given processor must be specified, attributes for different processors may not be mixed.

Field
Attribute
XCSB value
Description
A
 Program Memory Code Protect CFG_CP_ALL code protect all program memory
CFG_CP_OFF do not code protect any program memory
B
   CFG_CCP2_RC1 CCP2 function on RC1
CFG_CCP2_RB3 CCP2 function on RB3
C
 In Circuit Debugging CFG_DEBUG_ON In Circuit Debugger disabled
RB6 and RB7 are general purpose I/O pins
CFG_DEBUG_OFF In Circuit Debugger enabled
RB6 and RB7 are dedicated to the debugger
D
 Brown-out Reset voltage level CFG_VBOR_2_0 VBOR set to 2.0V
CFG_VBOR_2_7 VBOR set to 2.7V
CFG_VBOR_4_2 VBOR set to 4.2V
CFG_VBOR_4_5 VBOR set to 4.5V
E
 Split Brown-out Reset Config CFG_BOREN_1 MUST BE CONFIGURED IN CONJUCTION WITH BORSEN
with CFG_BORSEN_1 == BOR enabled and always on
with CFG_BORSEN_0 == BOR enabled during operation and disabled during sleep by hardware
CFG_BOREN_0 MUST BE CONFIGURED IN CONJUCTION WITH BORSEN
with CFG_BORSEN_1 == BOR controlled by software bit SBOREN (PCON,2)
with CFG_BORSEN_0 == BOR disabled
F
   CFG_MCLR_ON RE3/MCLR pin function is digital I/O, MCLR internally tied to VDD
CFG_MCLR_OFF RE3/MCLR pin function is MCLR
G
 Power-Up Timer CFG_PWRTE_ON power-up timer enable
CFG_PWRTE_OFF power-up timer disable
H
 Watchdog timer CFG_WDT_ON watchdog timer enable
CFG_WDT_OFF watchdog timer disable
I
 Oscillator CFG_EXTRC_CLKOUT EXTRC oscillator; CLKO function on OSC2/CLKO/RA6
CFG_EXTRC_IO EXTRC oscillator; port I/O function on OSC2/CLKO/RA6
CFG_INTRC_CLKOUT INTRC oscillator; CLKO function on OSC2/CLKO/RA6 and port I/O function on OSC1/CLKI/RA7
CFG_INTRC_IO INTRC oscillator; port I/O function on OSC1/CLKI/RA7 and OSC2/CLKO/RA6
CFG_EXTCLK EXTCLK; port I/O function on OSC2/CLKO/RA6
CFG_HS_OSC High Speed Crystal / Resonator (HS) oscillator
CFG_XT_OSC Crystal / Resonator (XT) oscillator
CFG_LP_OSC Low Power Crystal (LP) oscillator
J
 Split Brown-out Reset Config CFG_BORSEN_1 MUST BE CONFIGURED IN CONJUCTION WITH BOREN
with CFG_BOREN_1 == BOR enabled and always on
with CFG_BOREN_0 == BOR controlled by software bit SBOREN (PCON,2)
CFG_BORSEN_0 MUST BE CONFIGURED IN CONJUCTION WITH BOREN
with CFG_BOREN_1 == BOR enabled during operation and disabled during sleep by hardware
with CFG_BOREN_0 == BOR disabled
K
   CFG_IESO_ON Internal External Switch Over mode enabled
CFG_IESO_OFF Internal External Switch Over mode disabled
L
   CFG_FCMEN_ON Fail-Safe Clock Monitor enabled
CFG_FCMEN_OFF Fail-Safe Clock Monitor disabled