*** groups
code_group
code_sect 0000 02F8 CODE
event_tbl_sect 017C 01F0 CODE
process_inputs_code_sect 0274 0066 CODE
state_code_sect 02A7 024E CODE
i2c_code_sect 03CE 06C4 CODE
vclk_code_sect 0730 0000 CODE
queue_0_fifo_code_sect 0730 0066 CODE
queue_1_fifo_code_sect 0763 0066 CODE
usr_code_code_sect 0796 00B0 CODE
data_group
data_sect 0000 0018 DATA
process_inputs_data_sect 0018 0006 DATA
state_data_sect 001E 0011 DATA
i2c_data_sect 002F 001A DATA
vclk_data_sect 0049 0007 DATA
global_fifo_data_sect 0050 0001 DATA
queue_0_fifo_data_sect 0051 000C DATA
queue_1_fifo_data_sect 005D 000C DATA
usr_code_data_sect 0069 0000 INVALID
*** sections
code_section 0000 0000 INVALID
data_section 0000 0000 INVALID
usr_code_data_sect 0069 0000 INVALID
const_section 0000 008B DATA
data_sect 0000 0018 DATA
process_inputs_data_sect 0018 0006 DATA
state_data_sect 001E 0011 DATA
i2c_data_sect 002F 001A DATA
vclk_data_sect 0049 0007 DATA
global_fifo_data_sect 0050 0001 DATA
queue_0_fifo_data_sect 0051 000C DATA
queue_1_fifo_data_sect 005D 000C DATA
code_sect 0000 02F8 CODE
event_tbl_sect 017C 01F0 CODE
process_inputs_code_sect 0274 0066 CODE
state_code_sect 02A7 024E CODE
i2c_code_sect 03CE 06C4 CODE
queue_0_fifo_code_sect 0730 0066 CODE
vclk_code_sect 0730 0000 CODE
queue_1_fifo_code_sect 0763 0066 CODE
usr_code_code_sect 0796 00B0 CODE
code_section 0000 0000 INVALID
data_section 0000 0000 INVALID
usr_code_data_sect 0069 0000 INVALID
const_section 0000 008B DATA
0000 C
0000 INDF
0000 PS0
0000 RBIF
0000 RD
0000 TMR0_reset_val
0000 event_000
0000 fifo_ok
0000 i2c_busy_bit
0000 i2c_stat_ok
0000 ind
0000 mode_001_initial_state
0000 mode_009
0000 r_fifo
0000 s_event
0000 state_000
0000 vclk_VCG0
0000 vclk_event_id
0000 vclk_event_interval
0000 vclk_wrap_transition_bit
0001 DC
0001 INTF
0001 PS1
0001 TMR0
0001 WR
0001 event_001
0001 i2c_master
0001 i2c_pending_bit
0001 i2c_slave
0001 i2c_uses_vclk
0001 mode_001
0001 mode_009_initial_state
0001 r_tbl_base
0001 s_source_state
0001 state_001
0001 vclk_VCG1
0002 PCL
0002 PS2
0002 T0IF
0002 WREN
0002 Z
0002 clk_slew_dly
0002 data_valid_dly
0002 event_002
0002 i2c_hunting_bit
0002 s_target_state
0002 state_002
0002 vclk_VCG2
0003 NOT_PD
0003 PSA
0003 RBIE
0003 STATUS
0003 WRERR
0003 event_003
0003 i2c_read_cmd_bit
0003 r_tbl_len
0003 s_state_transition_func
0003 state_003
0003 vclk_VCG3
0004 EEIF
0004 FSR
0004 INTE
0004 NOT_TO
0004 T0SE
0004 TMR0_prescale_val
0004 event_004
0004 fsr
0004 i2c_SCL
0004 i2c_read_bit
0004 mode_009_event_tbl_len
0004 s_state_handler_func
0004 state_004
0005 PORTA
0005 RP0
0005 T0CS
0005 T0IE
0005 event_005
0005 i2c_SDA
0005 i2c_write_bit
0005 in_port
0005 state_005
0006 EEIE
0006 INTEDG
0006 PORTB
0006 RP1
0006 event_006
0006 i2c_SCL_port
0006 i2c_SDA_port
0006 i2c_start_bit
0006 i2c_stat_start
0006 i2c_stop_cond_read
0006 state_006
0006 vclk_VCG0_port
0006 vclk_VCG1_port
0006 vclk_VCG2_port
0006 vclk_VCG3_port
0007 GIE
0007 IRP
0007 NOT_RBPU
0007 event_007
0007 i2c_error
0007 i2c_stat_stop
0007 i2c_stop_bit
0007 state_007
0008 EEDATA
0008 event_008
0008 i2c_stat_read_complete
0008 state_008
0009 EEADR
0009 event_009
0009 i2c_stat_write_complete
0009 state_009
000A PCLATH
000A event_010
000A state_010
000A timer_reload
000B INTCON
000B event_011
000B state_011
000C event_012
000C state_012
000D event_013
000D state_013
000E event_014
000E state_014
000F CP_ON
000F event_015
000F state_015
000F tlen
0010 timer_event
0017 i2c_slave_addr
002A mode_001_event_tbl_len
0040 i2c_stat_sync_ok
0064 state_100
0065 state_101
0066 state_102
0067 state_103
0068 state_104
0069 state_105
006A state_106
006B state_107
006C state_108
006D state_109
006E state_110
006F state_111
0070 state_112
0070 taddr
0071 state_113
0072 state_114
0073 state_115
0080 event_i2c_data_read
0081 OPTION_REG
0081 event_i2c_data_written
0082 event_i2c_start_condition
0082 i2c_stat_prem_start
0083 event_i2c_stop_condition
0083 i2c_stat_missing_start
0084 event_transfer_failed
0084 i2c_stat_addr_mismatch
0085 TRISA
0085 event_transfer_complete
0085 i2c_stat_missing_ack
0086 TRISB
0086 event_read_block
0087 event_write_block
0088 EECON1
0088 event_ready
0089 EECON2
0089 event_busy
008A event_init_transfer
00C1 i2c_stat_prem_stop
00FF fifo_error
00FF in_port_mask
00FF out_port
00FF out_port_mask
3FF7 PWRTE_ON
3FFB WDT_OFF
3FFC LP_OSC
3FFD XT_OSC
3FFE HS_OSC
3FFF CP_OFF
3FFF PWRTE_OFF
3FFF RC_OSC
3FFF WDT_ON
data_sect 0000 0018 DATA
000C timer
000D delay
000E toggle_acc
000F toggle_cnt
0010 toggle_cnt2
0011 int_w_sav
0012 int_status_sav
0013 int_cnt
0014 xfr_cmd
0015 xfr_addr1
0016 xfr_addr2
0017 xfr_len
process_inputs_data_sect 0018 0006 DATA
0018 j
0019 mask
001A changes
001B PA_new_port_status
001C PA_port_status
001D PA_debounce_cnt
state_data_sect 001E 0011 DATA
001E mode_009_current_state
001E mode_current_state
001F mode_009_state_handler_func
0021 mode_001_current_state
0022 mode_001_state_handler_func
0024 mode
0025 event
0026 current_state
0027 target_state
0028 event_occured
0029 row_base
002B tmp_row_base
002D row_cnt
002E temp
i2c_data_sect 002F 001A DATA
002F shadow_port_A
0030 shadow_port_B
0031 i2c_data_in
0032 i2c_data_out
0033 i2c_bit_cnt
0034 i2c_dly_cnt
0036 i2c_own_vclk
0037 i2c_xfr_status
0038 i2c_xfr_err_cnt
0039 i2c_i2c_pc
003B i2c_i2c_status
vclk_data_sect 0049 0007 DATA
0049 vclk_vclk_pc
004B vclk_vclk_status
004C vclk_vclk_phase
004D vclk_vclk_cnt
global_fifo_data_sect 0050 0001 DATA
0050 xinval
queue_0_fifo_data_sect 0051 000C DATA
0051 queue_0_inval
0052 queue_0_outval
0053 queue_0_head
0054 queue_0_tail
0055 queue_0_buff
queue_1_fifo_data_sect 005D 000C DATA
005D queue_1_inval
005E queue_1_outval
005F queue_1_head
0060 queue_1_tail
0061 queue_1_buff
code_sect 0000 02F8 CODE
0000 init
0005 STF_M_init_transfer
0009 SMF_M_init_transfer
000A STF_M_ready
000C SMF_M_ready
000D STF_M_transfer_complete
000F STF_M_abort_transfer
0011 SMF_M_write_stop
0012 STF_M_wt_cmd
0016 SMF_M_write_cmd
0017 STF_M_wt_addr1
001B SMF_M_write_addr1
001C STF_M_wt_addr2
0020 SMF_M_write_addr2
0021 STF_M_wt_len
0026 SMF_M_write_len
0027 STF_M_rd_block
002F mrdb_1
0030 mrdb_9
0031 STF_M_rd_data
0039 mrdd_6
003B mrdd_7
003F mrdd_9
0040 SMF_M_read_data
0041 STF_M_wt_block
0044 STF_M_wt_data
004C mwtd_1
0054 mwtd_9
0055 SMF_M_write_data
0056 STF_S_init_transfer
005B SMF_S_init_transfer
005C STF_S_ready
005E SMF_S_ready
005F STF_S_wait_for_stop
0061 SMF_S_wait_for_stop
0062 STF_S_busy
0063 STF_S_rd_cmd
0067 SMF_S_read_cmd
0068 STF_S_rd_addr1
006C SMF_S_read_addr1
006D STF_S_rd_addr2
0071 SMF_S_read_addr2
0072 STF_S_rd_len
0079 SMF_S_read_len
007A STF_S_rd_block
007D STF_S_rd_data
0085 stf_srdd_1
008C stf_srdd_9
008D SMF_S_read_data
008E STF_S_wt_block
0096 srdb_1
0097 srdb_9
0098 STF_S_wt_data
00A4 stf_swtd_1
00A5 stf_swtd_2
00A6 SMF_S_write_data
00A7 master_write_test
00B2 master_read_test
00BD master_write_bad_test
00C8 master_read_bad_test
00D3 master_monitor_func_x0
00D4 master_monitor_func_x1
00D5 master_monitor_func_x2
00D6 master_monitor_func_x3
00D7 master_transition_func_x0
00D9 master_transition_func_x1
00DB master_transition_func_x2
00DD master_transition_func_x3
00DF slave_write_test
00E2 slave_read_test
00E5 slave_write_bad_test
00E8 slave_read_bad_test
00EB slave_monitor_func_x0
00EC slave_monitor_func_x1
00ED slave_monitor_func_x2
00EE slave_monitor_func_x3
00EF slave_transition_func_x0
00F1 slave_transition_func_x1
00F3 slave_transition_func_x2
00F5 slave_transition_func_x3
00F7 start
0147 loop_end
0148 int_serv
0152 int_s01
0156 int_s015
015E int_s02
0164 int_s03
0169 int_s04
0170 int_s05
0176 process_timer
017B lab8_5
017C $
event_tbl_sect 017C 01F0 CODE
017C exec_ind
0184 mode_009_event_tbl_base
0198 mode_001_event_tbl_base
026A mode_tbl
0272 mode_009_initial_state_handler_func
0273 mode_001_initial_state_handler_func
process_inputs_code_sect 0274 0066 CODE
0274 PA_process_inputs
027E PA_lab2_2
028C PA_lab2_4
0298 PA_lab2_5
0299 PA_lab2_6
02A2 PA_lab2_8
02A6 PA_lab2_end
state_code_sect 02A7 024E CODE
02A7 do_state_transition
02AE lab3_1
02BB lab3_5
02D1 lab3_9
02D9 lab3_end
02DA do_state_stable
02E8 process_mode_event
030B pme_lab_5
030C reread_event
030E lab7_1
030E process_events
032E vclk_vcs_20
033E vclk_vcs_30
034C vclk_vcs_40
035C vclk_vcs_50
035D vclk_vcs_90
035D vclk_vcs_95
0364 vclk_resume2_isr_0
0367 vclk_resume2_isr_1
036A vclk_resume2_isr_2
036D vclk_resume2_isr_3
0370 vclk_resume2_isr_4
0373 vclk_resume2_isr
0374 vclk_resume_isr
037E i2c_td_1_535
037F i2c_td_2_535
0388 i2c_td_3_535
0393 i2c_resume2_isr_0
0396 i2c_resume2_isr_1
0399 i2c_resume2_isr_2
039C i2c_resume2_isr_3
039F i2c_resume2_isr_4
03A2 i2c_resume2_isr_5
03A5 i2c_resume2_isr_6
03A8 i2c_resume2_isr
03AD i2c_resume_isr
03AD i2c_td_9_535
03B5 srv_02_534
03BB srv_04_534
03C1 srv_05_534
03C7 srv_06_534
03C8 srv_07_534
03CD lab7_8
03CD srv_09_534
i2c_code_sect 03CE 06C4 CODE
03CE i2c_xwait_clk_slew_dly_0
03D1 i2c_xwait_clk_slew_dly_1
03D4 i2c_xwait_clk_slew_dly_2
03D7 i2c_xwait_clk_slew_dly_3
03DA i2c_xwait_clk_slew_dly_4
03DD i2c_xwait_clk_slew_dly_5
03E0 i2c_xwait_clk_slew_dly_6
03E3 i2c_xwait_clk_slew_dly
03E9 i2c_xwait_data_valid_dly_0
03EC i2c_xwait_data_valid_dly_1
03EF i2c_xwait_data_valid_dly_2
03F2 i2c_xwait_data_valid_dly_3
03F5 i2c_xwait_data_valid_dly_4
03F8 i2c_xwait_data_valid_dly_5
03FB i2c_xwait_data_valid_dly_6
03FE i2c_xwait_data_valid_dly
0404 i2c_read_byte_master_task
0424 mrd_1_6
044F i2c_write_byte_master_task
0466 mwt_1_55
0471 mwt_2_55
0474 mwt_3_55
0496 mwt_4_55
049B mwt_5_55
04A3 i2c_write_stop_master_task
04BF busy_lab_127
04BF master_read_byte_blocking_entry_point
04CA busy_lab_131
04CF busy_lab_134
04CF master_write_byte_blocking_entry_point
04DB busy_lab_138
04DF busy_lab_140
04DF master_write_stop_blocking_entry_point
04EA busy_lab_144
04EE master_read_byte_entry_point
04F1 rdb_1_1
04FB master_write_cmd_entry_point
0500 wtc_1_1
050C master_write_byte_entry_point
050F wtb_1_1
051A master_write_stop_entry_point
051D wts_1_1
0527 i2c_read_byte_slave_task
052F ws_05_170
0534 ws_10_170
053B ws_11_170
0540 ws_12_170
0547 ws_14_170
054C ws_15_170
0556 slave_read_byte_entry_point2
0556 srdd_2_167
055B srdd_25_167
055F srdd_3_167
0562 srdd_4_167
0569 srdd_45_167
056D srdd_5_167
0574 srdd_55_167
0578 srdd_6_167
0585 srdd_65
0588 srdd_79
058E srdd_7_167
0593 srdd_8_167
0598 srdd_85_167
05A3 srdd_9_167
05A5 srdd_99_167
05A8 i2c_write_byte_slave_task
05B0 ws_05_229
05B5 ws_10_229
05BC ws_11_229
05C1 ws_12_229
05C8 ws_14_229
05CD ws_15_229
05D7 swtd_2_226
05DF swtd_3_226
05E2 swtd_4_226
05E2 swtd_5_226
05E7 swtd_6_226
05EC swtd_65_226
05F1 swtd_7_226
05F6 swtd_75_226
05FC swtd_8_226
0601 swtd_85_226
0605 swtd_9_226
0607 swtd_99_226
060A i2c_write_stop_slave_task
0612 ws_05_279
0617 ws_10_279
061E ws_11_279
0623 ws_12_279
062A ws_14_279
062F ws_15_279
0639 swtd_2_276
0641 swtd_3_276
0644 swtd_4_276
0644 swtd_5_276
0649 swtd_6_276
064E swtd_65_276
0653 swtd_7_276
0658 swtd_75_276
065E swtd_8_276
0663 swtd_85_276
0667 swtd_9_276
0669 swtd_99_276
066C i2c_wait_for_stop_slave_task
066E rsyn_0_326
0673 rsyn_1_326
067A rsyn_2_326
0681 rsyn_3_326
0688 busy_lab_342
0688 slave_read_cmd_blocking_entry_point
0695 busy_lab_348
069C rdc_8_164
069E rdc_9_164
069F busy_lab_353
069F slave_read_byte_blocking_entry_point
06AA busy_lab_357
06B1 rdb_8_164
06B3 rdb_9_164
06B4 busy_lab_362
06B4 slave_write_byte_blocking_entry_point
06C0 busy_lab_366
06C7 busy_lab_370
06C7 slave_write_stop_blocking_entry_point
06D2 busy_lab_374
06D9 busy_lab_378
06D9 slave_wait_for_stop_blocking_entry_point
06E4 busy_lab_382
06EB slave_read_cmd_entry_point
06EE rdc_1_164
06FA slave_read_byte_entry_point
06FD rdb_1_164
0708 slave_write_byte_entry_point
070B wtb_1_164
0716 slave_write_stop_entry_point
0719 wts_1_164
0723 slave_wait_for_stop_entry_point
0726 wsc_1_164
queue_0_fifo_code_sect 0730 0066 CODE
0730 queue_0_fifo_init
0733 queue_0_fifo_empty
0738 queue_0_fifo_full
0740 queue_0_fifo_read
0750 queue_0_fifo_write
vclk_code_sect 0730 0000 CODE
queue_1_fifo_code_sect 0763 0066 CODE
0763 queue_1_fifo_init
0766 queue_1_fifo_empty
076B queue_1_fifo_full
0773 queue_1_fifo_read
0783 queue_1_fifo_write
usr_code_code_sect 0796 00B0 CODE
0796 enter_situation_normal
079A enter_crisis_level_0
079E enter_crisis_level_1
07A2 enter_crisis_level_2
07A8 default_state_handler
07AF lab6_41
07B5 lab6_4
07B6 situation_normal_state
07BD lab6_51
07C3 lab6_5
07C4 crisis_level_0_state
07CB lab6_31
07D1 lab6_3
07D2 crisis_level_1_state
07D9 lab6_21
07DF lab6_2
07E0 crisis_level_2_state
07E7 lab6_11
07ED lab6_1
*** undefined symbols
MACINV